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FIR HDL Writer
Operating Systems |
FIR HDL Writer - FAQWhat is the FIR HDL Writer?The FIR HDL Writer generates a clear text Verilog HDL source code describing a FIR filter. This clear text code may be simulated in a Verilog Simulator, or synthesized to describe/create hardware (in the form of FPGA's or ASICs). The FIR HDL Writer generates a design file and a verification testbench (with impulse, step, and random responses). Design features include multiple channels, multiple coefficient sets, multiple clocks to perform the computation, interpolation, and decimation filters (using a polyphase decomposition). Why is this a beta release (what's not yet done)?The beta version of the FIR HDL Writer does not support multi-channel interpolation or multi-channel decimation filters. A warning will be issued, and the filter will be converted to a multi-channel single rate filter. You may manually padd the input for each channel with zeros to interpolate, or drop data after filtering to decimate. Expect support for this feature very soon. We don't yet have full documentation, and are looking at various installation methods, and some user interface issues. The designs generated have been simulated (with our self-checking testbench), and synthesized to FPGAs. Introductory pricing for licenses are $1795 during the beta period (till June 22, 2007), and $1995 afterwards. How do I install/run the FIR HDL Writer on my Windows XP system?
How do I install/run the FIR HDL Writer on my Linux system?
How do I install/run the FIR HDL Writer on my Mac OS X system?
How do I purchase/install a license?
Licenses may be purchased on-line at :
http://store.optunis.com/firhdldes.html
What's the gist of the license/maintenance policy?
Licensing for the FIR HDL Writer works similar to licensing in the EDA (Electronic Design Automation) industry. How do I contact Optunis about FIR HDL Writer?We're always glad to hear feedback from our customers.
Why do the windows look odd (on Windows systems)?This program was created using GNUstep cross platform libraries, and employ the OpenStep look and feel. GNUstep is a powerful cross platform object-oriented framework for desktop application development which originated on Unix systems. GNUstep is based on the OpenStep specification originally developed by NeXT and Sun and based on NeXTSTEP. Further information about OpenStep can be found here. GNUstep allows for various backends to deliver different themes (or skins) to the GUI elements. We are investigating different looks for the final release on windows. The tabs look strange in my Windows machineThe issue effects some Windows machines. GNUstep implements a set of routines (called the GNUstep Back-end) to interface to a various window system (Windows XP, X11, etc) Tabs are rendered using MinGW on the GNUstep Back-end for Windows, and may have white edges on them. How do I save, and restore my settings?Save settings with the save button. Load settings by selecting Document->Open. How do I load coefficients?Select the Coefficients tab. Click on the + button to load a set of coefficients from a file. Where are my output files?Select the Files and Testbench tab. Locations and names of output files are specified there. How do I simulate this design?Look in the generated report file for explicit commands to use for various simulators. Commercial Verilog simulators are availble from Cadence and Mentor Graphics. A free simulator called Icarus is available here.
Commercial Verilog simulators are available from Cadence, Synopsys, and Mentor Graphics. Where can I find timing diagramsAs of Beta 0.9 timing diagrams have not yet been made. To obtain timing info, use the port descriptions on the report file, run the verilog simulation, and view the results with a waveform viewer (such as GTKWave, SignalScan, or UnderTow). How do I synthesize to an FPGA?
Use ISE to synthesize to Altera FPGA's. Should I use Altera or Xilinx for my FPGA?Both vendors make excellent products. Since the FIR HDL Writer, you can generate your own clear text Verilog RTL design, and make your own best choice comparing resource utilization, speed, and cost. How fast do the targeted designs run?The designs are currently pipelined for use in FPGA's with built-in multipliers. We've observed fmax in the 300MHz range (plus and minus) depending on the FPGA selected, and routing resources available. Your results may vary. Useful Links for Hardware Design
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