FIR HDL Designer - version 0.9.0 (Beta)
---------------------------------------

(best viewed with a monospaced font)

date           : 2007-05-24 10:02:33 -0700
licensed user  : xxxxxxxx

this file      : log.txt
design file    : fir_design.v
testbench file : test.v
directory path : /xxxx/xxxx/xxxx/xxxx/


FIR HDL Design Report
---------------------

PORTS
------------------------------------------------------------------------------------
Name             : Type   : Description
---------------- : ------ : ---------------------------------------------------------------
clk              : input  : clock signal
rst              : input  : active high reset (enable must be high for rst to activate)
enable           : input  : active high enable
data_in          : input  : input data
data_out         : output : delayed input (used for cascading several FIR filters together)
fir_calc         : output : calculated FIR filtered result
coef_set_in      : input : select for coefficient set (time aligned with specific data_in) 
in_ch_num        : output : (time sliced) channel number for data_in
out_ch_num       : output : (time sliced) channel number for fir_calc
rdy              : output : active high indicator.  The FIR Filter will load date on the next rising edge clock.
                            To prevent loading data, set enable to low (before the next rising edge)
out_valid        : output : active high indicator.  The FIR Filter has produced an output.
------------------------------------------------------------------------------------


SETTINGS
input data bit width          : 16
number of input channels      : 1
throughput rate (clocks to perform a single computation for a single channel): 5
rate type                    : SINGLE RATE (input rate == output rate) 


data storage type             : registers
coefficient storage type      : inferred memory
reload circuitry              : NO
symmetry circuitry            : NO
COEFFICIENTS
Coefficient Report

# of coefficient sets         : 1
# of coefficients per set     : 35


minimum required bit width    : 13
minimum (set   0, index   13) : -689
maximum (set   0, index   17) : +4095


Coefficient bit width (set)   : 16
Calculated Maximum Resolution Output Bit Width (with reduced multipliers) : 38



MULTIPLIERS
full precision bit width : 32
multiplier dimensions    : 16x16
number of multipliers    : 7

reduced multiplier output precision : NO
bits removed from MSB               : 0
bits removed from LSB               : 0
MSB bit removal method              : truncate
LSB bit removal method              : truncate


OUTPUT
reduced output precision : NO
bits removed from MSB    : 0
bits removed from LSB    : 0
MSB bit removal method   : truncate
LSB bit removal method   : round (+ "0.5" if positive, -"0.5" if negative)



MISC

latency at TDL : 5
latency at multipliers : 8
latency at accumulator : 11



FIR HDL Testbench Report
------------------------

INFO
----------------------------------------------------------------------------------
Name            : Type     : Description
--------------- : -------- : -----------------------------------------------------
clk             :  signal  : clock signal 
clk_count       :  signal  : clock counter - keeps track of tick counts 
                :          : 
DUT             : instance : (Device Under Test) the FIR Filter being verified 
data_in         :  signal  : input to the FIR Filter 
fir_calc        :  signal  : output from the FIR Filter 
expected_result :  signal  : expected value from the FIR calculation (comparison point)
perform_match   :  signal  : indicates a comparison between expected and fir_calc results
----------------------------------------------------------------------------------

After simulating, if all tests pass, the message PASSED - ALL TESTS PASSED
is displayed in the simulator window


SIMULATION EVENT TIMES

clock period            : 100.000000
sim end (clk_count)     : 7000
sim impulse (clk_count) : 1000
sim step (clk_count)    : 3000
sim random (clk_count)  : 5000


SIMULATION COMMANDS

to run a simulation (with ModelSim)
   cd /xxxx/xxxx/xxxx/xxxx/
   vlog -work work fir_design.v
   vlog -work work test.v
   vsim -work work test.v
   run

to run a simulation (with VerilogXL)
   cd /xxxx/xxxx/xxxx/xxxx/
   verilog fir_design.v test.v

to run a simulation (with VCS)
   cd /xxxx/xxxx/xxxx/xxxx/
   vcs -R fir_design.v test.v

to run a simulation (with Icarus Verilog)
   cd /xxxx/xxxx/xxxx/xxxx/
   iverilog -o sim.out test.v fir_design.v
   vvp sim.out

to view waveforms (with GTKWave)
   gtkwave -f dump.vcd