FIR HDL Writer

Clear Text RTL

The FIR HDL Writer generates a (clear text Verilog HDL RTL source code) design file for FIR filters.

If you're an ASIC/FPGA designer, then you already know the benefits of clear text RTL. In fact, it's most likely your biggest request. After all, you want to own your design. You want the freedom to try it on different devices, and different vendors. You may want to customize certain internal processing, or make subtle modifications. Clear text RTL puts you back in the driver seat.

Simulation and Test Benches

Since the testbench and design files are clear text Verilog, RTL simulation is extremely fast, easy, and efficient. Some FIR Filter design systems require you to add various encrypted low level libraries with arcane protection schemes in order to simulate, or to simulate at the gate level.

A self checking Verilog testbench is generated, providing impulse, step, and random stimulus (across one or more channels), and verifies the results against pre-computed values. After all tests are simulated, if no errors are encountered, the message ALL TESTS PASSED is displayed (in your Verilog simulator).

FIR Designer Features

There are several design options available. You can specify

• Coefficients
  • Bit Width
  • Coefficient values are specified with a simple ASCII text file
  • Multiple Coefficient Sets
  • Coefficient Reload
  • Coefficient Reload - (direct random access to coefficient values)
• Input Data, Number of Channels, and Multiplier Precision
  • Input Bit Width
  • Number of (Time Shared) Channels
  • Multiplier Output Precision
• Data Rates
  • Single Rate
  • Interpolation
  • Decimation
• Computation and Resource Specification
  • Computation Speed (number of clocks to perform a computation)
  • Specify memory type (inferred memory) or flip-flops for data storage and coefficient storage
  • Symmetric Multiplier Reduction
    (pre-add the data values prior to multiplication to reduce the multiplier and coefficient storage utilization)
• Pipelined for excellent performance in modern FPGAs
• Testbench Specification
  • Impulse Amplitude
  • Step Amplitude and Length
  • Random Amplitude and Length
• Automatically Generated Custom Report File shows
  • design and testbench names and directory paths
  • all port names and functional descriptions for the design
  • user settings
  • informatation and recommendations regarding user settings
  • calculated latecies
  • primary signals for design instance for the testbench
  • simulation event times
  • commands to run the design and testbench on various simulators and waveform viewers

System Requirements

Supported Operating Systems

• Windows XP
• Linux
• Mac OS X

Supported Simulators / Waveform Viewers

• Cadence NC Verilog
• Mentor Graphics ModelSim
• Synopsys VCS
• Icarus Verilog + GTKWave

Supported Synthesis Tools

• Xilinx - ISE
• Altera - Quartus