Press Release - Date : May 31, 2007

Optunis Announces FIR HDL Writer v 0.9.0 Beta

Optunis is pleased to announce the FIR HDL Writer 0.9.0 Beta. FIR Designer is an Electronic Design Automation (EDA) tool used to generate clear text synthesizable Verilog Register Transfer Level (RTL) source code to make FIR filters (which may be synthesized to FPGA's and ASICs).

Design options include multiple channels, coefficient sets, interpolation, decimation, and resource utilization specifications. The designs are fully synchronous and registered to provide maximum clock frequencies. Clock rates in excess of 300Mhz have been observed with Stratix II and Virtex IV devices (using Quartus and ISE synthesis and place and route tools) from Altera and Xilinx.

Since verification has become a greater part of the work load for FPGA and ASIC developers, the FIR HDL Writer includes a self checking testbenches which performs impulse, step, and random tests.

The FIR HDL Writer is the first cross platform product released by Optunis, and runs natively on Windows XP, Linux, and Mac OS X.

A single user license for the FIR HDL Writer is available for $1795 during the beta period (till June 22, 2007). The FIR HDL Writer is compatible with Windows XP, Linux, and Mac OS X. Additional information is available at http://www.optunis.com/fir_hdl_writer/fir_hdl_writer_info.html

About Optunis:

Optunis was founded in 2005 to help scientists and engineers deal with the ever-increasing complexity in our field. Our goal is to provide tools to amplify your capabilities - because your time is important to us.

Press Contact: marketing@optunis.com